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Analog/mixed‑signal ic design engineer
0 à 1 an d'expérienceContact
Réf. OB2606291343
Née le 14/03/2000
75000 Paris
2000-03-14 https://www.ouvrierbtp.com/cv-candidat/2606291343/analog-mixedâ€-signal-ic-design-engineer Female Paris Ile de France France 75000 Paris
Née le 14/03/2000
75000 Paris
2000-03-14 https://www.ouvrierbtp.com/cv-candidat/2606291343/analog-mixedâ€-signal-ic-design-engineer Female Paris Ile de France France 75000 Paris
Langues
Persian
Azerbaijani
English
Turkish
French
Azerbaijani
English
Turkish
French
Centres d'intérêts
Analog IC design, Biomedical sensor interfaces, Ultra‑low‑power systems, RF front‑ends, Data converter architectures, Multicultural work environments
Ma recherche
Je recherche tout type de contrat, sur toute la région Ile de France, dans le Batiment.
Formations
12/2025 : Bac +5
Master 2 — Integration, Circuits and Systems Key topics: RF electronics, microelectronics, MEMS/NEMS, embedded systems, high‑performance ADC/DAC design, hardware signal processing.
Master 2 — Integration, Circuits and Systems Key topics: RF electronics, microelectronics, MEMS/NEMS, embedded systems, high‑performance ADC/DAC design, hardware signal processing.
12/2024 : Bac +5
Master 1 — Electrical Engineering for Communications & Information Processing Focus on communications, electrical/optical engineering, microelectronics, and emerging device technologies. Coursework taught in English.
Master 1 — Electrical Engineering for Communications & Information Processing Focus on communications, electrical/optical engineering, microelectronics, and emerging device technologies. Coursework taught in English.
12/2023 : Bac +3
Bachelor of Electrical Engineering Foundation in circuits, analog/digital electronics, semiconductors, control, and signal processing.
Bachelor of Electrical Engineering Foundation in circuits, analog/digital electronics, semiconductors, control, and signal processing.
Expériences professionnelles
05/2025 - 09/2025 : Analog IC Design Intern chez Aarhus University, Aarhus
Designed a fully integrated low‑noise, low‑power chopper amplifier for neural signal acquisition in 65 nm CMOS. Performed schematic design and simulations (AC, transient, noise, stability, PSS) and implemented chopping, ripple reduction, input‑impedance boosting and DC‑servo techniques in Cadence Virtuoso. Prepared documentation and reports detailing methodology and results.
Designed a fully integrated low‑noise, low‑power chopper amplifier for neural signal acquisition in 65 nm CMOS. Performed schematic design and simulations (AC, transient, noise, stability, PSS) and implemented chopping, ripple reduction, input‑impedance boosting and DC‑servo techniques in Cadence Virtuoso. Prepared documentation and reports detailing methodology and results.
Langues
Persian
Azerbaijani
English
Turkish
French
Azerbaijani
English
Turkish
French
Centres d'intérêts
Analog IC design, Biomedical sensor interfaces, Ultra‑low‑power systems, RF front‑ends, Data converter architectures, Multicultural work environments
Atouts et compétences
Cadence Virtuoso, Spectre, SPICE, Verilog‑A, Analog/Mixed‑Signal Design, CMOS Layout, Low‑Power Circuits, Post‑Layout Simulations, AFE Design, Verilog, C programming, MATLAB, Python (basic), RF Electronics, Data Converters, Sensor Interfaces, Biomedical Circuits, Mixed‑Signal Systems, Low‑Noise Low‑Power Chopper Amplifier (project), Capacitive Isolation System for AC Switch Control (project), Indoor Positioning System (WiFi+INS Fusion) (project), UWB Positioning Research (project)
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